As state-of-the-art computer systems and circuits evolve, there is a continuing need for higher performance bipolar junction transistors capable of operating at higher switching speeds, with increasing degrees of device integration, and with low rate of failure. There is also a continuing need to shrink or scale down device size to obtain improved device performance.
An attempt to form bipolar junction transistors with reduced lateral dimensions using self-alignment techniques is disclosed in an article by Armin W. Wieder entitled "Submicron Bipolar Technology: New Chances For High Speed Applications", IEDM, pp. 8-11, (1986). Another attempt to form bipolar junction transistors having self-aligned regions therein is disclosed in U.S. Pat. No. 5,721,147 to Yoon, entitled "Methods of Forming Bipolar Junction Transistors", the disclosure of which is hereby incorporated herein by reference. Referring now to FIGS. 1-4, another conventional method of forming a bipolar junction transistor includes the steps of forming an N-type epitaxial layer 10 (as a collector region) on a P-type substrate (not shown). Field oxide isolation regions 11 may also be formed in the epitaxial layer 10, using conventional techniques. A first polysilicon layer 12 may be formed on a face of the epitaxial layer 10 and on the isolation regions 11, as illustrated best by FIG. 1. This first polysilicon layer 12 may be formed as a P-type layer by implanting P-type impurities into the first polysilicon layer 12. A first oxide layer 13 is then formed on the first polysilicon layer 12. Referring now to FIG. 2, a masked etching step is then performed to selectively etch through portions of the first oxide layer 13 and first polysilicon layer 12 and expose the N-type epitaxial layer 10. A second oxide layer 14 may then be deposited on the exposed portion of the N-type epitaxial layer 10, as illustrated. A relatively highly doped extrinsic base region 15 may then be formed by out-diffusing dopants from the patterned first polysilicon layer 12 into the epitaxial layer 10. A more lightly doped base link-up region 16 may then be formed by implanting P-type dopants (e.g., B or BF.sub.2) through the second oxide layer 14 and into the epitaxial layer 10. The second oxide layer 14 may then be removed.
Referring now to FIG. 3, oxide spacers 17 are then formed on the etched sidewalls of the first polysilicon layer 12 and first oxide layer 13, as illustrated. P-type dopants are again implanted into the epitaxial layer 10 to form an intrinsic base region 18 therein. Here, the oxide spacers 17 and first oxide layer 13 act as an implant mask. Referring now to FIG. 4, an N-type emitter contact 19 is then formed on the intrinsic base region. This N-type emitter contact 19 may be formed by depositing an undoped layer of polysilicon, implanting N-type dopants (e.g., arsenic) into the undoped layer of polysilicon and then patterning the layer of polysilicon using conventional techniques. An annealing step may then be performed to cause out-diffusion of N-type dopants from the emitter contact 19 into the intrinsic base region 18, to define an emitter region 20 therein.
Unfortunately, because it may be difficult to accurately control the thickness of the above-described oxide spacers 17, it may also be difficult to control important transistor characteristics such as emitter-base junction breakdown voltage (BV.sub.ebo) current gain .beta., unit cutoff frequence f.sub.T, base resistance, perimeter punch-through voltage, etc. Moreover, because the base link-up region 16 may have a lower P-type doping concentration therein, the formation of thick oxide spacers 17 may cause the base resistance to be unnecessarily large. In addition, the characteristics of the intrinsic base region 18 may not be independently controllable since this region also receives dopants during the step of forming the base link-up region 16.
Thus, notwithstanding these prior art attempts, there continues to be a need for improved methods of forming bipolar junction transistors.